Conventionally, there has been employed a register file which is a storage apparatus which is a collection of storage devices and in which reading can be performed faster than in DRAM or SRAM as a register of a computer such as CPU or MPU. A circuit for this register file is designed to be small and to operate at high speed, and is configured so that diagnosis on manufacturing a semiconductor chip is performed at high speed and high efficiency, thereby achieving improvement in performance of the semiconductor chip and reduction in manufacturing cost.
A structure of a conventional basic register file is realized so that a write address decoder circuit 204, a read address decoder circuit 206 and a read select circuit 208 are added to a memory array 200 in an array structure where storage devices 202 are arranged as shown in FIG. 1.
Here, the storage devices 202 used for the register file have the following two types, each of which has a merit and a demerit.
(1) Master flip-flop only latch
(2) Flip-Flop in a master-slave structure
In other words, when a master flip-flop only latch is assumed as a storage device, there is a merit that it can made small in size but there is a demerit that a scan circuit cannot be formed therein. On the other hand, when a flip-flop in a master-slave structure is assumed as a storage device, there is a merit that a scan circuit can be formed therein but there is a demerit that the size is made twice or more than the master flip-flop only latch.
Here, the scan circuit connects in series storage devices in a semiconductor chip constituting a register file in a path different from that in a normal operation and constitutes a shift register, which operates only at the time of testing the semiconductor chip.
FIG. 2 shows a register file at a normal time, and exemplifies a case where the memory array 200 is constituted of (3×4)=12 storage devices in (address direction)×(data direction) for simplified explanation. As for data writing in the memory array 200, the write address decoder circuit 204 in FIG. 1 decodes a write address to select four storage devices 202 in the data direction in a specific register and to write 4-bit data in parallel. As for data reading from the memory array 200, a read address decoder circuit 106 in FIG. 1 decodes a read address to select a read bus, which is a collection of read lines, from the four storage devices 202 in the specific register by the read selector circuit 208 and to read 4-bit data in parallel.
FIG. 3 shows a shift register constituted of the scan circuit at the time of testing when the flip-flop in the master-slave structure is assumed as the storage device, where the storage devices 202 in the memory array 200 are connected in series in a path different from that in the normal operation to constitute a shift register. This scan circuit can be used to observe the state of the storage devices inside the semiconductor chip, which is originally invisible, or to perform defective inspection (diagnosis) at high speed and high efficiency at the time of manufacturing a semiconductor chip in a demonstration test. That is, how many scan functions the storage devices in the semiconductor chip can have is a key as to whether the high test efficiency and diagnosis efficiency can be realized.
FIG. 4 shows a master flip-flop only latch storage device used for the memory array 200 in FIG. 1, which is constituted of an input inversion inverter 210, a pair of connected-in-parallel gates 212 and 214 constituting a dual gate which is turned ON in response to a data clock CK0 and its inverted data clock XCK0, a pair of alternately feedback-connected inverters 216 and 218 constituting a latch 215, and an inversion output inverter 220. The operation thereof turns ON the gates 212 and 214, for example, in response to the data clock CK0 and XCK0, latches data D inverted in the inverter 210 into the latch 215, and inverts and outputs the same in the inverter 220.
FIG. 5 shows a master-slave type flip-flop storage device used for the memory array 200 in FIG. 1, where connection is established for the latch storage device circuit unit 222 identical to that in FIG. 4 from a shift input SI via the inverter 224 and the gates 226 and 228 constituting a dual gate to the latch 215 and a latch 234 which alternately feedback-connects the gates 230 and 232 constituting a dual gate and the gates 236 and 238, and the output inversion inverter 240 are provided from the latch 215 to a shift output SO. Here, the inverter 210, the gates 212, 214, the latch 215 and the inverter 220 constitute the master flip-flop used at the normal time as in FIG. 2, and the inverter 220, the gates 212, 214 and the latch 215 constitute the flip-flop in the master-slave structure used as the shift register for testing as in FIG. 3.
The operation at the normal time of the flip-flop storage device in the master-slave structure in FIG. 5 is as in the time charts of FIGS. 6A to 6E. At the normal operation, the clock CK1 and the clock CK2 for scan shift are fixed at level 0 as in FIGS. 6B and 6C without being input, and only the latch storage device circuit unit 222 operates. In other words, after the data D in FIG. 6D rises to level 1, the gate 212 is turned ON in response to the clock CK0 of FIG. 6A, the data is held in the latch 215 and inverted in the inverter 220 to perform latch operation where the output Q in FIG. 6E is at level 1.
The scan circuit operation such as testing is as in the time charts of FIGS. 7A to 7F. The clock CK0 of FIG. 7A is fixed at level 0 without being input, the clock CK1 of FIG. 7B is first input by 1 clock to turn ON the gate 230, and the data in the latch 215 is copied to the latch 234, and is inverted in the inverter 240 so that the data is output to the shift-out SO in FIG. 7F. After a sufficient time has elapsed, the clock CK2 is input by 1 clock as in FIG. 7C. A time until the clock CK 2 is input is several-hundred times of the system operation cycle depending on the performance of the tester. When the clock CK2 is input by 1 clock to turn ON the gate 226, the data in the shift-in SI in FIG. 7D is set to the latch 215 to be the output Q in the inverter 220 in FIG. 7E. Hereinafter, this is repeated to realize the scan operation of the shift register as shown in FIG. 3.
In designing the register file, when the master flip-flop only latch is assumed as the storage device, the size thereof can be reduced, causing reduction in chip area and further improvement in performance and reduction in cost. However, since the scan circuit cannot be formed therein, it is necessary to additionally design a dedicate circuit outside the register file in place of the scan circuit for chip diagnosis or demonstration test. Thus, a gate is added to a critical path at the normal operation, causing reduction in performance. Further, since it causes increase in chip diagnosis pattern and diagnosis time for defective inspection, causing reduction in efficiency for demonstration test, increase in manufacture cost is finally caused.
Also, when the flip-flop in the master-slave structure is assumed as the storage device, the scan circuit can be internally formed as in FIG. 3 so that the diagnosis and demonstration test for the register file can be easily performed. However, as compared with being constituted of the master flip-flop only latch, the size becomes twice or more. This is because the master flip-flop only latch storage device is realized by the 10 transistors while the flip-flop storage device in the master-slave structure in FIG. 5 requires 22 transistors. This causes reduction in performance and increase in cost. When actually designing the chip, depending on various specifications or conditions, some register files employ the master flip-flop only latch storage devices for the size at the expense of diagnosis efficiency and demonstration test efficiency, alternatively other register files employ the flip-flop storage devices in the master-slave structure for the scan at the expense of the size. When the size or the manufacturing efficiency is considered as trade-off point, the difference therebetween is significantly large.
The fact that options of the storage device structure for the register file are extremes is a significant problem in designing a semiconductor chip. The storage device structure of the register file has to be determined at the initial time of design, and its determination is remarkably important. If the determination is erroneous and some change is required in the middle of the design, a large change in mounting is caused and terrible delay may occur. As described above, the fact that the options of the storage device structure for the register file are extremes is a significant problem.
It is an object of the present invention to provide a register file for enabling a scan circuit to be assembled only by slightly increasing the size of a semiconductor chip, thereby achieving high test diagnosis efficiency.